1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device that generates an output enable signal used for a read operation.
2. Description of the Related Art
Generally, semiconductor memory devices including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) receive a command signal and an external clock signal from an external controller and perform diverse operations. For example, at a read operation, a semiconductor memory device outputs a data synchronized with an internal clock signal in response to a read command. The semiconductor memory device may include a circuit for generating the internal clock signal by coinciding the operation timings of the external clock signal and the internal clock signal with each other and use the internal clock signal in performing the diverse operations. A Delay Locked Loop (DLL) and an output enable controller may serve as such a circuit.
First, a delay lock loop generates an internal clock signal by delaying an external clock signal by a set time. Generally, the semiconductor memory device takes some delay time to transfer a clock signal. Therefore, the semiconductor memory device generates an internal clock signal by compensating for the delay time to an external clock signal, and such an operation of the semiconductor memory device is referred to as ‘locking’.
Secondly, the output enable controller synchronizes a read command synchronized with an external clock signal, with an internal clock signal. The clock signal, that a read command is synchronized with, is changed from the external clock signal to the internal clock signal, and the change of a synchronization signal from one clock signal to another clock signal is referred to as ‘domain crossing’. The output enable controller performs the domain crossing operation to generate an output enable signal. The output enable signal includes, for example, CAS latency information CL. Here, the CAS latency information CL may represent time information from a moment, when a read command is applied, to a moment, when a data is to be outputted, by taking one period of the external clock signal as a unit time.
The semiconductor memory device operates in such a manner that a data to be synchronized with the external clock signal is outputted at a desired moment after the receipt of the read command by using the delay lock loop and the output enable controller.
FIG. 1 is a block diagram illustrating an output enable controller of a conventional semiconductor memory device.
Referring to FIG. 1, the output enable controller includes a counter reset signal generation unit 110, an initialization unit 120, a DLL clock counting unit 130, a delay unit 140, an external clock counting unit 150, a count value latch unit 160, and a count value comparison unit 170.
The counter reset signal generation unit 110 synchronizes a reset signal RST with a DLL clock signal CLK_DLL and generates a first reset signal RST_DLL for resetting the DLL clock counting unit 130.
The initialization unit 120 provides the DLL clock counting unit 130 with an initial count value INT<0:2> that corresponds to CAS latency information CL. For example, a 3-bit code signal is used as the initial count value INT<0:2> in FIG. 1. The following Table 1 shows initial counting setup values and the initial count value INT<0:2>, wherein the initial counting setup values are set in response to CAS latency information CL 3 to CL 6 and the initial count value INT<0:2> is outputted from the initialization unit 120 in response to the initial counting setup values.
TABLE 1CLinitial counting setup valueINT<2>INT<1>INT<0>35101441005301162010
In Table 1, the initial counting setup value and the initial count value INT<0:2> may be differently set to the CAS latency information CL depending on the configuration and the circuit design of the semiconductor memory device.
The DLL clock counting unit 130 performs a counting operation in response to the first reset signal RST_DLL. In other words, the DLL clock counting unit 130 outputs a DLL clock count value CNT_DLL<0:2> that is counted from the initial count value INT<0:2> in response to the DLL clock signal CLK_DLL based on the first reset signal RST_DLL. For example, when the initial count value INT<0:2>, i.e., the initial counting setup value, is set to 4 based on the CAS latency information CL, the DLL clock counting unit 130 outputs a DLL clock count value CNT_DLL<0:2> that is counted from 4 in response to the DLL clock signal CLK_DLL. For example, a typical 3-bit counter may be used as the DLL clock counting unit 130.
The delay unit 140 models the extent of delay between the DLL clock signal CLK_DLL and an external clock signal CLK_EXT. The delay unit 140 delays the first reset signal RST_DLL and outputs a second reset signal RST_EXT.
The external clock counting unit 150 performs a counting operation in response to the second reset signal RST_EXT. In short, the external clock counting unit 150 outputs an external clock count value CNT_EXT<0:2> that is counted in response to the external clock signal CLK_EXT based on the second reset signal RST_EXT. The initial count value of the external clock counting unit 150 is set to ‘0’ differently from that of the DLL clock counting unit 130. In other words, after the second reset signal RST_EXT is enabled, the external clock count value CNT_EXT<0:2> is counted from ‘0’ in response to the external clock signal CLK_EXT. Here, a general 3-bit counter may be used as the external clock counting unit 150 the same as the DLL clock counting unit 130.
The count value latch unit 160 latches the external clock count value CNT_EXT<0:2> in response to a read command signal RD and outputs a latched external clock count value LAT_CNT<0:2>. The read command signal RD is a pulse signal that is synchronized with the external clock signal CLK_EXT and enabled in response to the applied read command.
The count value comparison unit 170 compares the DLL clock count value CNT_DLL<0:2> with the latched external clock count value LAT_CNT<0:2> and generates an output enable signal OE that is enabled at a moment when the two values become the same. The output enable signal OE is a signal synchronized with the DLL clock signal CLK_DLL, and it is a resultant signal obtained by synchronizing the read command signal RD inputted in synchronization with the external clock signal CLK_EXT with the DLL clock signal CLK_DLL. The output enable signal OE also reflects the CAS latency information CL.
Meanwhile, high-speed, light-weight, and low-power of semiconductor memory devices are being developed to satisfy consumers' needs. The conventional output enable controller, however, may obstruct the development of high-speed light-weight, and low-power semiconductor memory devices.
In the first place, as the operation frequency of a semiconductor memory device increases, the CAS latency value increases as well. A counter that constitutes the DLL clock counting unit 130 and the external clock counting unit 150 is designed depending on the CAS latency value. In short, when the CAS latency value becomes great, the counter also is to be designed to count the great number. For example, 4-bit counter operates more slowly than a 3-bit counter, and the operation speed of the counter becomes slow as the CAS latency value increases. Also, the count value comparison unit 170 also operates slowly as the number of bits to be compared is increased. This obstructs the high-speed operation of the semiconductor memory device.
Also, a counter occupies a relatively greater area than other circuits. Therefore, as the CAS latency value increases, the area of the counter increases as well, and this obstructs the development of small semiconductor memory devices.
Next, since the conventional output enable controller has a structure of latching the external clock count value CNT_EXT<0:2> at a moment when the read command signal RD is enabled, the DLL clock counting unit 130 and the external clock counting unit 150 are to perform a counting operation at least until the read command signal RD is enabled. In short, a counter that receives the external clock signal CLK_EXT and a counter that receives the DLL clock signal CLK_DLL continue to perform the counting operation until a read command is applied. This means that power may be continuously consumed until the read command is applied, and this may obstruct the implementation of low-power semiconductor memory devices.